COMPUTER LOGIC - 2017/8

Module code: COM1031

Module provider

Computer Science

Module Leader

CHEONG TOOK C Dr (Computer Sci)

Number of Credits

15

ECT Credits

7.5

Framework

FHEQ Level 4

JACs code

I100

Module cap (Maximum number of students)

N/A

Module Availability

Semester 1

Overall student workload

Independent Study Hours: 106

Lecture Hours: 24

Laboratory Hours: 22

Assessment pattern

Assessment type Unit of assessment Weighting
Coursework GROUP CW 40%
Examination EXAMINATION - 2 HOURS 60%

Alternative Assessment

An individual assessment will be set to replace the group coursework.

Prerequisites / Co-requisites

None

Module overview

To introduce the fundamental principles of digital logic, circuits and systems starting with symbolic logic through to the concept of logic gates to the structure and operation of digital logic circuits and systems. This module provides an understanding of the underlying computer architecture and internal operation of computer systems.

Module aims

To introduce the fundamental principles of digital logic, circuits and systems starting with symbolic logic through to the concept of logic gates to the structure and operation of digital logic circuits and systems.

Learning outcomes

Attributes Developed
Develop familiarity with combinational logic operations and design of combinational logic circuits
Apply the principles of analysis and design of simple circuit systems
Use number systems to perform simple binary arithmetic
Summarise the basic structure of a computer system and understand their function
Reason about the operation and performance of memory caches and simple virtual memory subsystems

Attributes Developed

C - Cognitive/analytical

K - Subject knowledge

T - Transferable skills

P - Professional/Practical skills

Module content

Indicative content includes:

• Combinational Logic

     o Circuit Implementations AND,OR, NAND, NOR, XOR.

     o Implementing logic functions

     o Circuit design using basic gates such as an OR gate from NAND gates

     o Adders – half adders and full adders.

Computer arithmetic: integer and floating point representations; 1’s and 2’s complement; arithmetic operations

• Synchronous sequential logic

     o Latches o Flip Flops

     o Analysis of sequential circuits: state tables, state diagrams, finite state machines

• Registers

     o Registers with parallel load

     o Shift registers

     o Bit manipulations

• Low level microcontroller programming

     o Hardwired implementation, instruction decoding

     o Interrupts o Implementation of traffic lights

     o Interaction with other electronic components such as 7segment display

• Counters

• Synchronous and Asynchronous operation

• Control Unit (CU)

• Data Processor (ALU)

• Bus system

• The memory unit

      o Design various types of memory using standard memory ICs

      o Memory Interleaving

      o Cache Memory

      o Virtual Memory

Methods of Teaching / Learning

The learning and teaching strategy is designed to:

The fundamentals, principles and theories for Computer Logic will be delivered in the lecture, whereas the lab sessions and the coursework will provide the students an opportunity to put in practice the lessons learnt.

The learning and teaching methods include:

44 contact hours in weeks 1-11, consisting of:


2 hours of lectures per week
2 hour lab session per week


Additionally, there will be a 1 hour drop-in surgery during office hours. The drop-in surgery will give students the opportunity to ask questions to support their self-study.

A diagnostic test will be scheduled that will ensure the student has assimilated the material during the course.

Students will be expected to spend the remainder of the 150 hours on self-study

Assessment Strategy

The assessment strategy is designed to provide students with the opportunity to demonstrate

Thus, the summative assessment for this module consists of:

• Group coursework (40%) to demonstrate an understanding of the operation of a basic computer and the relevance of binary arithmetic in computer hardware. Deadline: 1st week in Christmas holidays (Week 11+1). Submission method: SurreyLearn (online). This will test LO2, LO3 and LO4.

• 2 hours of unseen examination (60%). It will consist of two parts. The first part is compulsory and will examine the general understanding of the student in Computer Logic. The second part will test a deeper understanding of computer logic and students are required to select two out of three questions. This will assess all LOs.

Formative assessment and feedback

Each lab session will provide an opportunity to provide feedbacks to students. Feedbacks will also be provided for the coursework. A diagnostic test will be scheduled that will ensure the student has assimilated the material during the course.

Reading list

Reading list for COMPUTER LOGIC : http://aspire.surrey.ac.uk/modules/com1031

Please note that the information detailed within this record is accurate at the time of publishing and may be subject to change. This record contains information for the most up to date version of the programme / module for the 2017/8 academic year.